1. Field of the Invention
This invention relates to digital circuitry and more particularly to a logic gate useful as a building block in bipolar digital circuit devices. Digital gates are primitive circuits used for performing boolean functions on electronic signals. They are frequently employed in complex devices having a large number of elements to perform specified logic functions. One of the limiting factors in a logic gate is the speed of operation. Complex logic functions involving any circuits are ideally performed in a minimum amount of time and consume a minimum amount of power. There is always a trade-off between power and speed. What is needed is a circuit which maximizes speed of operation for a given power dissipation.
2. Description of the Prior Art
There are numerous types of primitive logic gates, that is basic logic gates which serve as system building blocks. They are generally classified by characteristics of the circuit. For example, transistor transistor logic (TTL) involves the use of at least two transistors, generally constructed employing bipolar technology, in series to conduct a signal and to perform a primitive logic function such as a NAND or a NOR function. Emitter coupled logic (ECL) employs transistors wherein the emitters are coupled and saturation of the transistors is inhibited to increase switching speed. Many proposals have been made for enhancing the speed of logic gates. However, the simplest and most straightforward proposals, such as those built around a single transistor, often suffer from the inherent problem of inability to operate fast over wide temperature ranges due to changes in the base emitter voltage with temperature.
Referring to FIG. 1, there is shown one prior art embodiment of a primitive logic gate for use in an inverting OR function. This logic gate is generally referred to as a direct coupled transistor transistor logic gate (DCTTL). A description of DCTTL is found in "Direct-Coupled Transistor Transistor Logic: A New Performance LSI Gate Family," D. E. Fulkerson, IEEE Journal of Solid State Circuits, Volume SC-10, page 110 (April 1975). A DCTTL logic gate 10 comprises a first transistor Q.sub.A, a second transistor Q.sub.B coupled between a first node and a second node with a load resistor R.sub.L coupled between the first node and the voltage source and a small fan-out resistor R.sub.S coupled between the second node and the ground reference. Critical to the fast operation of this gate are clamping diodes, such as Schottky diodes D.sub.A and D.sub.B coupled between the base electrode and a collector electrode (node 1) of each of the transistors Q.sub.A and Q.sub.B. Output is through the connection at node 1. But for the clamping diodes D.sub.A and D.sub.B, the circuit would operate extremely slowly. The clamping diodes prevent full saturation of the transistors Q.sub.A and Q.sub.B so that a single transistor switching function is possible. The small fan-out resistor R.sub.S in addition to enhancing the fan-out ability at node 1, helps to reduce the likelihood of malfunction over a wide temperature range. This function may be referred to as current hogging prevention.
Referring to FIG. 2, there is shown another prior art circuit generally referred to as a current mode logic gate 12. A description of CML is found in "A 1500 Gate, Random Logic Large Scale Integrated (LSI) Masterslice," R. J. Blumberg and S. Brenner, IEEE Journal of Solid State Circuits, Volume SC-14 No. 5, page 818 (October 1979). A first transistor Q.sub.A and and a second transistor Q.sub.B are coupled between a first node 1 and a second node 2. The first node 1 serves as the output terminal for the gate 12, and a load resistor R.sub.L is coupled between the voltage source coupling V.sub.CC and the first node 1. A current source C.sub.S, such as a resistor or a suitably biased transistor, is coupled between the second node 2 and the ground reference. The current source Q.sub.S in combination with a voltage reference transistor Q.sub.R which is coupled also to the second node 2 establishes the threshold at which the gate 12 switches. The reference transistor Q.sub.R is coupled between the second node and the voltage source coupling V.sub.CC. The current mode logic is related to emitter coupled logic in that it is a non-saturating logic family.
While there are advantages to each of the prior art circuits, there is also room for improvement. The DCTTL gate 10 draws a high base current, which is a distinct disadvantage in applications wherein such a gate forms a basic building block in a complex circuit. The CML logic gate 12 requires an external voltage reference for the reference transistor Q.sub.R and frequently for the current source C.sub.S. Thus, extra wiring is required with its concomitant disadvantages, and it also runs the risk of input device saturation at high temperatures.